mm-Wave Systems for High Data Rate Wireless Consumer Applications

ISM spectrum at 60GHz has attracted attention for possible high-speed applications in wireless communications for well over ten years. However, no high volume applications have emerged. Despite progress in mm-wave ICs, the power and cost of these efforts have not reached the level needed for mass deployment. This paper summarises the ARC funded GLIMMR project which aims to remedy this situation by designing systems on silicon that have both low cost and low power. In particular, the paper presents design work done to date that indicate that silicon (particularly SiGe) is on the cusp of being able to provide economical mm-wave systems

Influence of Dry Soil on the Ability of Formosan Subterranean Termites, Coptotermes formosanus, to Locate Food Sources

The effect of barriers of dry soil on the ability of Formosan subterranean termites, Coptotermes formosanus Shiraki (Isoptera: Rhinotermitidae), to construct tunnels and find food was evaluated. Termite movement and wood consumption in a three—chambered apparatus were compared between treatments with dry soil in the center container and treatments where the soil in the center container was moist. When a wood block was located in the release container, termites fed significantly more on that block, regardless of treatment or soil type. In the treatment with dry clay, none of the termites tunneled through the dry clay barrier to reach the distal container. When termites had to tunnel through a barrier of dry sand, topsoil, or clay to reach the sole wood block, there was no effect on wood consumption for the sand treatment, but there was significantly less feeding on wood in the treatments with dry topsoil or clay. When foraging arenas had a section of dry sand in the center, the dry sand significantly reduced tunneling in the distal section after 3 days, but not after 10 days. There was a highly significant effect on the ability of termites to colonize food located in dry sand. Only one feeding station located in dry sand was colonized by termites, compared with 11 feeding stations located in moist sand

Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

In this study, the authors present a design optimisation case study of D-type flip-flop timing characteristics that are degraded as a result of intrinsic stochastic variability in a 25 nm technology process. What makes this work unique is that the design is mapped onto a multi-reconfigurable architecture, which is, like a field programmable gate array (FPGA), configurable at the gate level but can then be optimised using transistor level configuration options that are additionally built into the architecture. While a hardware VLSI prototype of this architecture is currently being fabricated, the results presented here are obtained from a virtual prototype implemented in SPICE using statistically enhanced 25 nm high performance metal gate MOSFET compact models from gold standard simulations for pre-fabrication verification. A D-type flip-flop is chosen as a benchmark in this study, and it is shown that timing characteristics that are degraded because of stochastic variability can be recovered and improved. This study highlights significant potential of the programmable analogue and digital array architecture to represent a next-generation FPGA architecture that can recover yield using post-fabrication transistor-level optimisation in addition to adjusting the operating point of mapped designs

A phase-locked loop reference spur modelling using Simulink

Phase-Locked Loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioural modelling are developed, where the focus is on the random noise aspect of these modules. In this paper, we introduce charge pump and Phase/Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs. In addition, the effect of the VCO gain, loop filter order and loop bandwidth on the reference spurs level are taken into consideration. The proposed model was implemented in Simulink and showed less than ±3% error when compared to transistor level simulations from Cadence Spectre. Using this approach a 10 time improvement in simulation speed was achieved compared to transient analysis from Cadence Spectre.Noorfazila Kamal, Said Al-Sarawi, Neil H. E. Weste and Derek Abbot

Low cost reactively matched broadband GaAs MMIC power amplifier for airborne applications

A highly efficient, single stage broadband power amplifier was designed and fabricated in WIN Semiconductor 0.10 μm GaAs technology. Reactive matching networks were used to optimize the broadband performance in Class AB topology. This was obtained by iterating the load and source fundamental impedances to achieve the highest PAE with the second harmonic load termination short circuited. Measured results at 10 GHz show a saturated output power of around 27 dBm, drain efficiency as high as 71.2% and a PAE of 64.1% with a small signal gain of 16.5 dB and a large signal gain of 12.9 dB. The amplifier has excellent broadband characteristics and the highest reported drain efficiency (DE) of over 50% between 7-13 GHz.Aaron Pereira, Said Al-Sarawi, Neil Weste, Vincenzo Carrubb